BICMOS Circuits

The conventional CMOS circuits are of greater importance in all the digital circuits which require a low power specifications. The low power specifications desire a lower driving capability and thus CMOS can drive sufficiently the moderate loads and thus delay will be less. 

But there can be a situation in the designs where there may be requirement for the higher drive strength circuits. There can be loads of higher capacity and the time taken by the CMOS circuits will be really large and thus the circuit operation degrades. As an example consider the below circuit of SRAM. Here the memory bit is connected to the bit line BL. This bit line is of higher capacitance and to write a bit to the cell, requires charging or discharging this bit line of higher capacitance. If we use a CMOS inverter here, then there will be degradation in the delay performance.

Thus we need higher driving capability in some scenarios. This can achieved by using Bi-CMOS circuits. Below is the example of a merged Bi-CMOS circuit.

In the above circuit, the BJT transistors are used to at the driving stage and they will drive the current of pmos or nmos with a gain of beta times higher. Thus driving capacity is increased and thus delay performance will be better. Only disadvantage with this Bi-Cmos is the area overhead and the fabrication complexity.