BICMOS Circuits

The conventional CMOS circuits are of greater importance in all the digital circuits which require a low power specifications. The low power specifications desire a lower driving capability and thus CMOS can drive sufficiently the moderate loads and thus delay will be less. 

But there can be a situation in the designs where there may be requirement for the higher drive strength circuits. There can be loads of higher capacity and the time taken by the CMOS circuits will be really large and thus the circuit operation degrades. As an example consider the below circuit of SRAM. Here the memory bit is connected to the bit line BL. This bit line is of higher capacitance and to write a bit to the cell, requires charging or discharging this bit line of higher capacitance. If we use a CMOS inverter here, then there will be degradation in the delay performance.

Thus we need higher driving capability in some scenarios. This can achieved by using Bi-CMOS circuits. Below is the example of a merged Bi-CMOS circuit.

In the above circuit, the BJT transistors are used to at the driving stage and they will drive the current of pmos or nmos with a gain of beta times higher. Thus driving capacity is increased and thus delay performance will be better. Only disadvantage with this Bi-Cmos is the area overhead and the fabrication complexity.

FINFET BASICS

 

Lets look at the Samsung s5 series smart phones featuring in the market. These phones come with the Qualcomm’s latest 2.5GHz quad-core Krait processor. So, high performance eh!! 

Correct. 

These high performer processors will rule the industry for a maximum duration of one or two years.

After that??

 People will look for a change. Crowd need smart phones having less leakage and thus long battery life, high performance and intelligent in built features.
So, silicon industry wants to shrink the device as much as possible and tries to fit as many features as possible in the single SoC. At the same time,industry does not want to compromise with the performance. If  we look at the Krait processor that I mentioned above, it is having the mos devices with 28nm technology with the Hpm process. For the next generation of smart phones where is the way?The way is to shrink the device even further and make it go beyond 20 or 10 nano-meter?
No!!!!
This has reached an obstacle. A big obstacle indeed.!!
What is that obstacle?


Lets look at the three essential things for grading any transistor(switch),

•   Active current(Ion)

• Leakage current(Ioff)

• Performance(switching)

As the channel length decreases, the above three parameters will show degradation for MOSFET and hence the transistor looses its grade.Also, with the decrease in channel length we see the decrease in the quantity Ion/Ioff ratio, which is not tolerable for good designs.These things are creating obstacles.Moreover, if we look at the threshold trend for a transistor switching, we see interesting facts.       

               

Technology	Operating Voltage
250nm	2.5V
180nm	1.8V
130nm	1.3V

     

               but for 90nm its not 0.9V…its 1.2V!!!

This interesting trend shows that as the technology shrinks, we are not able to achieve the shrink in the operating voltages after 90nm. This is because of the fact that with the lower technology, leakage increases and thus it is difficult to discriminate between ON and OFF states, which eventually affects the decreasing trend with the operating voltage.



Short channel effects are becoming more significant as we shrink the channel length. (mainly DIBL)

So, what is solution?, solution to overcome this obstacle!!

Here it comes.

                                                           

• We should have better control  over the channel length of the transistor.
• Instead of controlling the channel from one direction we have to control it from more possible directions. 
• To shrink below 25nm we should go for 3D structure of transistor instead of planar MOSFET.

All above mentioned points are possible through, FinFET!!

Structure of FinFET

From the above structure it is very clear that, we are controlling the device in a 3D manner. Instead of holding a pipe(channel) with your tip of the finger like in MOS, you are holding the pipe(channel) with your hand(your fingers encircling and gripping the pipe) and thus having more control.

With the above structure we can have less leakage and thus we can still continue to shrink the channel length. 

Characteristics of FinFET

With the above characteristics, we can infer that, current equations of FinFET will be similar to MOSFET.

We will be encountering the different W value in the equation of current.

This is because we have the effective width of the transistor.

The width of a finFET (i.e. the width of the area controlled by the

gates), is defined as: Wgate = 2×Hfin+Wfin.

FinFET Layout

What are the new parameters of FinFET netlist?

• Fin pitch which is unique to FinFET
• Fin thickness.
• 2xfin_height+finthickness= channel width

Parasitics involved with FinFET

• Due to the non planar structure more parasitic are involved in the FinFets compared to the planar mosfets.
• The coupling capacitance between the  fin-shaped channel extension and other parts of the circuit is much larger than that in the planar MOSFET.
• The resistance of the narrow long channel extension is also larger than the traditional one as it is having small area of cross section.

Lets look at the advantages and concers of FinFET.

So, What is the conclusion???

The baton has been already handed over to FinFETs from MosFETs in the lower technologies involving 25nm and below.

Since the characteristics of FinFETs are well satisfied in terms of leakage, operating voltage and scalability, semiconductor companies have invested a lot on FinFETs. 

The manufacturing of products with FinFETs will be seen from 2013 year end. 

The scalability of products can be continued with FinFETs till 5nm and this will be accomplished by 2025.

The Integrated Circuits

Our generation has witnessed the fun of making things faster and at the same time smaller. We tried and touched every corner of life where miniaturization and better performance is possible. There is a genius behind all these miniaturization. There is a genius hand to make everything perform better.This genius controls all the fun stuffs including the control over a flight carrying thousands of people, control over the complex surgical operations on the human body, control on the modelling of super fast cars like Ferrari and this list goes on and on. And who is this tiny little guy controlling everything? Yes. There he is. The small little integrated circuit always known as "the IC". 

And where can we find this guy? Its easy. He is everywhere. He is inside a little car running on the busy honking traffic on earth and at the same time he is also there in the satellite travelling in deep silence. He is a cutie little black guy and has legs based on the work he does. Sometimes he will be with only four legs if he is doing tiny tasks and sometimes he will stretch it out to become a guy with almost forty eight legs doing all the complex operation in this world. This guy has become omnipotent by controlling everything in this world,
, omniscient by knowing everything from mechanical to musical things, and thus omnipresent to make everything faster.

Bow to this guy who is behind all the scenes.